This project utilizes the I2C bus for communication among all computer nodes and sensors. The microcontrollers and microprocessors used on this project must support either Slave I2C Device Operation, or Multi-Master Arbitrated I2C Device Operation.
The connector used for attachment to the main flight computer is a 6/7 pin, JST XA series connector. For the design of slave devices, any locking, mechanically secure connector may be used, provided that a cable can be made which interfaces with this JST XA series connector. This connector supplies 12v, 3.3V, 5V, GND, SDA, SCL and a GPIO. Up to 3 amps may be drawn through the 3.3v and 5v traces, however, it is suggested that this limit not be reached.
|White Star Bus|
|Pin||v1 6-pin Cable||v2 7-pin Cable||v3 8-pin Cable||Latch|
The I2C signals received from the Master are already pulled up to 3.3v. If your device requires the I2C bus to interface at 5 volt levels, please use a buffer IC, or a discrete circuit similar to the following: http://www.nxp.com/news/backgrounders/bg_esc9727/index.html. Buffer ICs are available from NXP in easy-to-use DIP packages.
The following Microprocessors are compatible with this I2C standard:
The I2C bus is a standard which has been championed by NXP for communicating simple data across short distance using low powered Microprocessors and similar devices. The bus has limits on length which are based on Bus Capacitance limits. In the case of our device, the capacitance limit is roughly 400 pico-farads. This means that the total length of cable connecting the Main Flight Computer to all secondary devices must be less than 1 meter unless buffers are used.
The I2C bus can support up to 128 slave devices, using 7 address bits. Address bits are transmitted as bits [7:1] of the first byte transmitted following a bus Start condition. The 0th bit is the data-direction bit, which indicates whether a master device wishes to request a read or a write operation. If the 0th bit is a 0, then the operation is a write, If the 0th bit is a 1, then the operation is a read.
During a write operation, the master device transmits data 1 byte at a time. After each byte, the slave acknowledges reception of the byte. If the slave does not acknowledge, the master does not continue to transmit. During a read operation, the slave takes control of the bus, and transmits data 1 byte at a time. After each byte, the master acknowledges reception. If the master does not acknowledge, the slave releases the bus.
The following documentation may be of some use in learning about the I2C bus:
The documents listed above include more complex examples which are required to gain a complete understanding of how I2C communication occurs. At a minimum a basic understanding of start and stop bits are required.
In this mode, the Master device is transmitting data to a slave. The master initiates communication by sending a start signal, followed by the 7-bit device address, followed by a binary “0” indicating that the mode is “Write.” The slave addressed then ACKs this transmission. The following bytes are sent, post-pended by an ack signal from the slave, acknowledging receipt of the preceding byte. If the slave device is not able to receive more data, it may send a NACK, or Not Acknowledge, indicating that no more bytes may be received. Otherwise, the Master may, at its leisure, send a Stop signal. The specifics of this transaction depends on the software on the master device, and the defined behavior of the slave device.
In this mode, the master device receives data from a slave. The master initiates communication by sending a start signal, followed by the 7-bit device address, followed by a binary “1” indicating that the mode is “Read.” The slave addressed then ACKs this transmission. At this point, the slave device takes control of the I2C bus, and writes a byte of data, which must be acknowledged by master device. This continues until the master fails to acknowledge a transmission. On this condition, the slave relinquishes control of the bus, and the master may transmit a stop signal.
This mode is common when reading memory locations from a slave device. A “data pointer” register must be loaded with a data pointer location before data may be read. In order to do this, the Master transmits a Start followed by the Address, and a binary “0” indicating write mode. The next byte or bytes contains information to be placed in the “data pointer” register. Then, instead of transmitting a stop condition, the master simply transmits another “Start.” This is known as a “Repeated Start,” and is recognized independently by more intelligent I2C devices (Simple devices simply recognize this behavior as though it were the first start). The master then transmits the slave address followed by a “1” indicating read mode. Data is then read from the location indicated by the pointer value written previously.
In the documentation referring to I2C communication, we will use the following conventions. Data Transfer is to be noted as follows:
<Abstract Data>+NotAbstractData ; Verbatim Data ; …
Bytes are separated by semicolons (;), Abstract data are enclosed by Greater-Than and Less-Than symbols (< and >), Non-abstract data to be appended to abstract data follows this with a plus sign, while Verbatim data is simply noted. Binary Verbatim Data will not be prepended by notation, Hexadecimal data will be prepended by “0x”, and Decimal Data will be prepended by “0d”.
|Wire Ratings 1)|
|Gage||Voltage Drop/m @ 50mA||Voltage Drop/m @ 2A||Ohms/km||Ampacity in Open Air|
We will be ordering both 22 gage and 30 gage for bus connections, use PTFE Extruded insulation.